3D integrated eWLB /FO-WLP technology for PoP & SiP

The trends for smartphone and other mobile devices are more than ever for integration and lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices including internet of things (IoT) and wearable electronics (WE) are; higher performance designs, lower power consumption, lower cost, smaller form factor, thinner profile and higher level of integration. The emerging of advanced of silicon node technology down to 7/10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products push the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die, 3D PoP and 3D SiP applications with eWLB/FO-WLP technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including IoT/WE and MEMS/Sensor. Assembly process details and mechanical reliability characterizations are to be discussed with component and board level reliability results. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multi layer RDL and 2/2um fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on 3D eWLB-PoP / eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.