The level-0 trigger processor for the NA62 experiment

The NA62 experiment at the CERN-SPS is designed to study the K + → π
⁺
νν ultra-rare decay using a high intensity hadron beam and detecting its decay products. The lowest level (Level-0, L0) trigger processor represents a crucial component in reducing the event rate, estimated to be about 10 MHz for most of the sub-detectors which form the trigger, by a factor 10 with a maximum admitted latency of 1 ms. For the realization of the trigger selection, two different approaches were developed. A first project is fully based on FPGA, in which the whole logic for data selection is hardware programmed, while the second one joins an off-the-shelf PC to the FPGA for greater flexibility in trigger programming. Development, test results and performances during NA62 data taking will be presented.