Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

We report In
0.53
GaAs-channel gate-all-around FETs with channel width down to 7nm and L
g
down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g
m
by 25% compared to InAs S/D. A g
m
of 1310 µS/µm with an SS
sat
of 82mV/dec is achieved for an L
g
=46nm device. At this L
g
, a record I
on
above 200µA/µm is obtained at I
off
of 100nA/µm and V
ds
=0.5V on a 300mm Si platform.