High bandwidth low power interposer interconnect challenge, design, and validation in 3D silicon stacked interconnect (SSI) technology

This paper describes the characteristics of interposer interconnects in 3D silicon stacked interconnect (SSI) technology in comparison to traditional silicon interconnects. It explores unique near end crosstalk (NEXT) and far end crosstalk (FEXT) behavior of simple interposer interconnect structure with simulation results. Six different routing structures were investigated for I/O density and signal integrity trade-off with emphasis in timing impact due to crosstalk. Analysis shows that the four routing structures with lower I/O density meet timing requirement set for 625MHz, whereas the remaining two routing structures with higher I/O density fail. The routing structure that demonstrates the best trade-off was implemented in a SSI technology test chip. Lab data shows that the timing impact from simultaneous switching noise (SSN) is less than 20% of timing budget at 625MHz targeted operating frequency.