Optimization design of the high speed loopback channel

In this paper, a novel design for a test application board connection method is presented with its signal integrity analysis and optimization. The objective of the optimization is to support over 30 Gbps data rates with very high signal integrity performance and mechanical flexibility. The full channel includes a test board, connectors, cables and an interposer connecting components together. This design allows single ended and differential high speed digital signals to be easily connected and disconnected from the test PCB through an interposer. Special concerns are given to analyzing the impact of mechanical deformations from practical installations to the signal delivery quality, such as the air gap generated by the interposer interfaces and the partial touching of the ground pin to the ground hole in the interposer housing. These effects have seldom been studied or addressed. Full wave finite element based methods are employed to model the parasitic properties of different parts of the design. Equivalent circuits are used to understand the signal transmission mechanisms. The TDR impedance path is utilized to help locate problems. Based on our analysis, optimizations are applied to achieve a high performance high speed loopback channel design.