Low-power PTL-based multiplexer design in ±0.9V 32nm dual-gate Si FinFET

Continued CMOS scaling has led to various issues in efficient implementation of both digital ans well as analog circuits. The possibility of adding additional gates to have a better control of the channel region has opened up a new door of opportunities for circuit designers aiming at sub-65nm designs. This paper presents the design of multiplexers at 32nm technology node using Si-FinFETs. Shorted-gate configuration is employed for each dual-gate transistor. Performance evaluation of the designed circuits was carried out using HSPICE simulations, and the results demonstrate the superiority of FinFET-based designs.