Fine-grained 3-D CMOS concept using stacked horizontal nanowire

To continue miniaturization of Integrated Circuits (IC), 3-D CMOS approaches using layer-layer, die-die and wafer-wafer stacking were proposed. Although these approaches achieve incremental density benefits compared to 2-D CMOS, they exhibit limited scaling, low yield, variability and thermal management challenges. We propose a radically different fabric concept for 3-D CMOS using stacked horizontal nanowires (SN3D) on a single die. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D's physical framework, and bottom-up material filling based manufacturing techniques are also central to our approach. Our initial projections reveal tremendous benefits; for full-adder design SN3D's density benefits are 14.6× and 5.5× over state-of-the-art 2-D CMOS and transistor-level monolithic 3-D respectively.