A Chip-level Redundant Threading (CRT) scheme for shared-memory protection

Chip-level Redundant Threading (CRT) is a generic approach employed in multi-core architectures to meet reliability or functional safety requirements of applications. Critical tasks are concurrently executed on several processing elements (PEs). Most approaches follow the fault detection and containment approach by employing a Sphere-of-Replication (SoR) on a fixed and hard-wired set of elements (PEs, memory regions). Execution and verification of tasks is bounded to this SoR set. The rigidity of design-time chosen PEs has a number of disadvantages. To enable more flexibility, in this work Flexible CRT Sets (FCRTS) are used. FCRTS are a hardware-based and run-time configurable approach. Three arbitrary PEs, which execute the same task set, are chosen at run-time. The verification functionality is implemented within shared components. In order to protect shared-memory, an extended memory controller is introduced. The method is architecture independent i.e. choice of PEs or target memory technology. It has a small footprint of just 7.2% in registers and 6.2% in LUTs when synthesized for a FPGA. Moreover, the performance penalty for critical tasks is only 17% and uncritical tasks do not experience any performance degradation.