Comparative study of WL driving method for high-capacity NAND flash memory

In this work, we demonstrated comparative study of the WL driving method in 256-Gb VNAND with 16KB page size. The fixed pulse width (FPW) which uses the fixed WL pulse width with incremental voltage has a large tPROG due to the decreased Vth shift in the later ISPP loop. The incremental pulse width (IPW) which incrementally increases the programming voltage and pulse width overcomes the small Vth shift problem in the later loop. In addition, the optimization methods for FPW and IPW are presented to obtain a small tPROG considering the narrow Vth distribution of NAND cell after programming operation. The comparison of the WL driving methods is performed by HSPICE simulation using the 0.25-μm PTM model with the parasitic RC in 16KB page size.