A completely efficient charge recovery adiabatic logic content addressable memory

This paper presents the design of a complete Energy Efficient Charge Recovery Adiabatic Logic Content Addressable Memory using the energy recycling principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell but the decoders which drives the bit lines and word lines are realized by using different adiabatic logic structures such as Complementary Pass Transistor Adiabatic Logic (CPAL), Split-level Charge Recovery Logic (SCRL), Two Level Adiabatic Logic (2LAL), Quasi-Adiabatic Logic, Positive Feedback Adiabatic Logic (PFAL), Two Phase Adiabatic Static Clocked Logic (2PASCL), Pre-resolve and Sense Adiabatic Logic (PSAL), Efficient Charge Recovery Adiabatic Logic (ECRL), etc., In this paper, we propose an innovative complete ECRL CAM cell built with ECRL bit line drivers and word line drivers. Thus charges of node capacitances on these lines along with that in the cells are well recovered. An evaluation is made between the conventional CAM Architecture and the proposed ECRL CAM Architecture. The simulation results of a 4×4 adiabatic logic Complete ECRL CAM proves to be better with a power saving of 65% than the conventional CAM. The circuits are designed using 180nm CMOS technology with a power supply of 1.8V using Cadence Virtuoso.