A Unified Framework for Analysis and Design of a Digitally Current-Mode Controlled Buck Converter

Mixed-signal current-mode control (MCMC) implementation has been gaining popularity, because of the tuning flexibility using the digital voltage controller G
_c
(z) along with the fast-changing analog current controller. Generally a continuous-time frequency-domain approach is adopted for the design of G
_c
(z); however, this method often fails to capture sub-harmonic, more generally the fast-scale instability due to finite discretization effects. This paper derives approximate discrete-time models and proposes a unified framework to derive closed-form stability conditions and discrete-time small-signal models of a synchronous buck converter under MCMC. Considering the effects due to finite output-voltage sampling and the effective series resistance (ESR) of the output capacitor, the stability boundary in MCMC is found to be significantly restricted compared to its analog counterpart. Further, design methods are proposed to enhance stability boundary with improved transient performance by tuning the controller directly in the digital domain. A buck converter prototype is made, and the MCMC technique is realized using an FPGA device. Analytical predictions are verified experimentally.