Design Considerations for Output Capacitance Under Inductance Mismatches in Multiphase Buck Converters

Interleaving is a technique that is commonly used due to its inherent reduction of current ripple and filter capacitance size. However, optimal interleaving is only achieved when the switching cells are identical. Variations of the filter inductance, which are caused by the manufacturing process or magnetic material properties, may lead to the total current ripple of all phases significantly larger than that of the ideal case in steady state, and slow down the energy transfer speed during the transient response. Consequently, in order to meet the voltage ripple and dynamic response requirements of multiphase converters, the calculation of the output capacitor under inductance mismatches has to be reconsidered, which has been rarely mentioned previously. This paper proposes a method to estimate the effect of inductance mismatches on output capacitance selection from two aspects including steady state and transient state. The proposed methodology enables mathematical expressions that allow us to calculate the maximum value of the capacitor considering nonidealities. Monte Carlo simulation is also used during the analysis by varying all of the inductors' values with respect to tolerance and distribution type to identify the worst case values in real applications, according to this approach, the principle of when the worst condition happens is summarized. Simulated and experimental results of a four-phase buck converter are presented in this study. Good agreement between the estimates and the measured values is demonstrated.