Design of digital logic cells on InAlN/GaN heterostructure

The article addresses design and development of logic gates and circuits fabricated on InAlN/GaN/Sapphire heterostructure employing an in-house technology process. Designed circuits are intended to execute the fundamental Boolean logic operations as well as the memory function covered by RS latch circuitry. The paper describes the complete design flow of logic cells, investigation and statistical simulations of their expected electrical parameters and full-custom layout representation design that will be used in the final monolithic fabrication process as a template for lithographic masks. Moreover, the development of scalable HSPICE behavioral model of standalone high electron mobility transistors (HEMT) used in the electrical simulations. Finally, pros and cons of the proposed solutions as well as challenges that need to be tackled in the future research are discussed.