Applications Of A Bit-serial Floating-point Complex Multiplier-accumulator For High-speed Digital Signal Processing

This paper deals with the problem of building compact, high- speed, fault-tolerant digital signal processors which utilize the bit-serial floating-point complex multiplier-accumulator (CMAC) as a processing element. Two target applications will be described in this paper - the Fast Fourier Transform (FFT) and the block least mean square (BLMS) adaptive finite impulse response (FIR) filter. The present study is intended as a starting point whereby the features implemented in the CMAC can be used in the design of other types of processing elements, and these will serve as a library of macrocells from which Advanced digital signal processors can be constructed with fast turnaround time.