A Novel System in Package with Fan-Out WLP for High Speed SERDES Application

A novel multi-chips Fan-out Wafer Level Package (FOWLP) with fine pitch Cu pillar bumps was presented to accommodate volumes of I/O requirements on a BGA organic substrate. Due to the manufacturing limitation, cost and reliability consideration of fine-pitch BGA substrate, chips with extremely fine pitch RDL routing (width/space=2/2um) and a 2.nD wafer level carrier was integrated as system-in-package (SiP) to resolve I/O capacity issue. Besides, multi-chips with small die size connected through wafer-level RDL was also developed to resolve low yield issue of large chip in advanced wafer process. In this paper, a comprehensive design methodology was introduced to cover fan-out WLP interconnection and BGA substrate design. A test vehicle built in TSMC N16 process was presented to verify the design methodology. With fully consideration on signal integrity (SI) and power integrity (PI), hundreds of interconnection I/Os with 4Gbps speed were achieved. Besides, high speed SERDES with 25Gbit/sec data rate was also verified to enable high speed and high bandwidth data center application.