Cost-effective multi-standard video transform core using time-sharing architecture

This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm CMOS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.