A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above

As the CMOS technology advancing rapidly, it becomes urgent to find a solution toward the suppress of rising leakage current. In recent researches, the optimization of MOS length was reported to decrease 30% subthreshold leakage current at the sacrifice of only several percent dynamic power and active area. Besides, Dual-Vth method was proposed to compromise the leakage current and the slew-rate (SR) performance. In this paper, the proposed 2×VDD output buffer with a novel PVTL (Process, Voltage, Temperature, Leakage) compensation circuit takes advantage of combining the two methods mentioned above to achieve 75% subthreshold current reduction in cutoff region, and better SR with the gate leakage trade-off. The proposed design is all-corner simulated at 800 MHz data rate and a 20 pF load given 1.05 V/1.8 V supply voltage using in a typical 28 nm CMOS process to justify the performance of the proposed compensation circuit.