A high performance sensing scheme for CMOS DRAMs

CMOS DRAMs which were first introduced commercially in the 256Kb DRAM generation have proven their advantages in power and performance, and are expected to be the future trend. In CMOS DRAMs, the half-V
DD
bitline sensing scheme — is widely used in the current generation of 1 Mb DRAMs. However, the half-V
DD
sensing scheme suffers a performance degradation as V
DD
is reduced. Starting with the 4 Mb DRAM generation, device reliability concerns resulted in the reduction of the on-chip power supply voltage to about 3.3 V from 5 V without any significant change in the device threshold voltages. The reduction in the internal power supply voltage lowers the precharge level in the half-V
DD
sensing scheme such that the overdrive on the transfer gate during the charge transfer becomes smaller, resulting in a long signal development time. This is avoidable if the immediate wordline boosting can be used, but this approach is difficult to achieve because of device reliability conccrns in scaled-down device dimensions. This paper describes a new sensing scheme in which the bitline is precharged to about 2/3V
DD
for a PMOS array
³
.