The MIT database accelerator: 2K-TRIT circuit design

The computational speed of a conventional von Neumann computer architecture is limited primarily by the data path bottleneck between the memory and the central processing unit (CPU). One solution to this problem is to eliminate the separation between the CPU and memory by moving the processor functions directly into the memory. The Database Accelerator (DBA) chip is an attempt to merge these two functions by incorporating high density content-addressable memory (CAM) in a multi-purpose parallel processor architecture. The DBA chip can be used as a conventional CAM with arbitrary word lengths and depths supporting arithmetic comparison, approximate matching, and other relational operations. There are a variety of additional applications which exploit the architecture of the DBA chip. [1]