A memory-based, arbitrarily adjustable CMOS digital delay circuit

Many important fields for the application of semiconductor ICs (e.g. digital communication networks, factory automation, office automation) are governed by processing digital data streams. Often these data streams are split into parts, which are processed separately. Afterwards usually synchronization is necessary, because different latencies occur in each processing unit. A delay circuit, which is adjustable within wide boundaries and applicable to a wide frequency range, would be useful for these applications. A recent paper <1> describes the realization of an adjustable delay circuit with a misted shift register and CCD approach. Application is however restricted to the audio range. Circuits which operate up to the video range <2> offer only a small programming range and usually have a high power dissipation. In this paper a memory-based concept for an arbitrarily adjustable, digital delay circuit and an experimental CMOS chip are presented. The basic idea of our solution is to replace the data shifting as in shift registers or CCD solutions by the shifting of a pointer to the wordlines of a memory. Only a small percentage of the data are shifted in addition, to ensure simple control circuitry for the programmable delay. The 60k-transistor chip can be programmed via a 12bit programming word, to realize any delay from 1 to 4096 clock cycles for a 4bit wide data word. Correct operation has been verified in the range from 3 kHz to 30 MHz. Thus the circuit is suited for audio as well as video applications.