An algorithm generating all rectangular duals for VLSI floor-plan

The concept of rectangular duals[1-4] provides an interesting approach to VLSI floor-plan in terms of a hierarchical design strategy. In order to determine the shape and relative position of each functional block (or “macro”), the approach uses more global information concerning not only interconnection requirements among functional blocks but also the total chip area, as compared with the conventional approaches, such as force-directed[5] and min-cut[6] methods. Moreover, this approach has a possibility to output a more area efficient floor-plan than the one by means of the so-called slicing structure[7,8], although it is harder to devise an efficient algorithm for this approach.