A self-test scheme for embedded memories using the coupling fault model

For VLSI chips with large embedded RAMs the inclusion of logic to generate patterns for complex fault models becomes worthwhile and even necessary. This is appealing for a number of reasons: required testing time otherwise is significant, more complex fault models are applicable, some of the necessary logic is already required on-chip for logic functions, and the additional logic is a small percentage of the chip logic. A number of methods have been proposed to generate test patterns on-chip, such as inclusion of a random pattern generator, storing the patterns in a ROM, and inclusion of special purpose logic to actually generate the patterns. Randomly generated test patterns require a large number of patterns to achieve even stuck-at fault coverage for a RAM (1J. Including all of the patterns a RAM needs in a ROM requires too much area. Special purpose logic to generate test patterns [2,3,4] has only used patterns that test for the stuck-at fault model or an ad hoc list of possible faults. However, this method can be extended to more complex fault models.