Scalable modeling of resistive losses 1n on-chip interconnects at mm-wave frequencies

This paper presents a systematic modeling methodology to capture the frequency-dependent resistive losses in on-chip interconnects due to the conductor skin and proximity effects. We have developed scalable closed-form expressions for the frequency-dependent resistance that are accurate over a wide range of dimensions applicable across different integrated circuit process nodes and over the broad frequency range from DC to 110 GHz. We demonstrate the modeling methodology for an example on-chip coplanar waveguide (CPW) interconnect structure and validate the models through measurements of a fabricated chip.