A 1.27mW 20Gbps 1:16 DEMUX with a symmetrical-edge-delay sense amplifier

A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data edges caused by the set-reset (SR) latch in the Sense-Amplifier-Based Flip-Flop, a new slave latch controlled by the clock is proposed which reduces delay and improves sensitivity considerably. A new type of CMOS logic 2:16 DEMUX is also proposed which can save about 20% area and 15% power consumption compared with the conventional structure. The power consumption of DEMUX is only 0.36mW at the date rate of 10Gb/s and 1.27mW at 20Gb/s. The proposed structure is based on Global Foundry 65nm CMOS process.