A hardware security solution against scan-based attacks

Scan based Design for Test (DfT) schemes have been in wide use to increase the testability of digital circuits. The main objective is to ensure that nodes in the Circuit Under Test (CUT) are controllable and observable. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation. In this work, a new method is presented to protect the sensitive information from attackers using scan chains. The access through the scan chain to the circuit containing the secret information has been severely limited to reduce the risk of a scan-based attack. To ensure the testability of the circuit, a built-in self-test utilizing an LFSR is considered. The proposed scheme can be used as countermeasure against side channel attacks with a low area overhead as compared to the reported solutions.