CALPAN: Countermeasure against Leakage Power Analysis attack by normalized DDPL

This paper proposes novel techniques against Leakage Power Analysis (LPA) attack on Dual-Rail Precharge Logic (DDPL) which is a Differential Power Analysis (DPA) resistant logic style. DDPL is first applied with sleep transistors technique and second with Normalization technique by which the Cryptosystem is made LPA resistant. Security metrics used for assessing the proposed logic styles are the leakage power and Coefficient of Deviation (CoD). By analyzing the leakage power traces secret key can be extracted, as the leakage power is data dependent. The leakage power dissipated by the Cryptosystem cannot be avoided completely but it can be reduced by which LPA attack can be avoided. To avoid LPA attack, leakage power should be made independent of data that is getting processed in the Cryptosystem. This paper concentrates on leakage power analysis of DDPL NAND applied with novel techniques and defines the leakage power and CoD. The logic styles are implemented and analyzed using Cadence© GPDK 45nm technology node. In the proposed method sleep transistor technique is applied to DDPL by which the power consumption is double the normal DDPL but the data dependency CoD has been reduced by 20% and with the novel Normalized DDPL technique, power consumption is reduced by 30% and the CoD has been reduced by 89.4% which implies that the power traces are made equal for all the input combinations by which LPA attack can be avoided. The power traces are measured at various temperatures by which dependency of Logic style on temperature i.e., thermal Stability is also studied.