Implementation for minimization of computation time of partial products for designing multipliers

Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay of adders, low power consumption, area which is conflicting constraints of speed etc. Our designs propose tradeoffs among computational time, latency and throughput of Vedic digital multiplier. This paper presents the high speed and low power multiplier logic design using Vedic multiplication method. The simulations have been carried out in Xilinx simulator for timing waveform simulation and a CMOS layout of Vedic multiplication is implemented in microwind layout simulator tool for analysis of power dissipation using 50nm technology.