High speed low-power true single-phase clock divide-by-16/17 dual-modulus prescaler using 130nm CMOS process with a Vdd of 1.2V

In this paper, the performance of a high speed CMOS TSPC divide-by-16/17 dual modulus prescaler is analyzed using 350nm, 250nm, 180nm and 130nm CMOS technologies. In this work, the supply voltage (Vdd) used for 350nm technology is 3.3V, the Vdd used for 250nm is 2.5V and a 1.2V supply for both 180nm and 130nm technologies. The divide-by-16/17 dual modulus prescaler is constructed using TSPC D-Flip-Flops. The experimental result shows that, the CMOS TSPC divide-by-16/17 dual modulus prescaler implemented using 130nm CMOS technology with a supply voltage of 1.2V is capable of operating up to 6GHz frequency and power consumption is 1.4mW at the maximum operating frequency under 1.2V supply. The simulation result shows that CMOS TSPC divide-by-16/17 dual modulus prescaler implemented using 130nm CMOS process with 1.2V Vdd reduces the power consumption by 40% compared to 180nm CMOS process with 1.6V Vdd.