A new adaptive PLL to reduce the lock time in 0.18µm technology

A 900MHz frequency synthesizer is presented in this article. The purpose of the proposed architecture is to minimize lock time in Phase-Locked Loops (PLLs). The basic idea behind this topology is using a larger loop bandwidth and gain during the frequency switching transition and shifting gradually the loop bandwidth to the normal value after the PLL is locked. The structure has been simulated by HSPICE software in a TSMC 0.18um technology at the supply voltage of 1.8V.