A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET

A 3-tap 64 Gb/s NRZ transmitter using a quad-rate architecture is designed in 16 nm FinFET. The design incorporates circuit techniques and topologies that take into account device properties specific to FinFET process. A 4:1 MUX consisting of static CMOS pulse generators and a tailless CML multiplexing stage is used at the final stage of serialization. An on-chip regulator provides power to the pulse generators and CMOS clock buffers. A phase error correction circuit corrects the phase errors of the four-phase clocks generated by an LC-PLL. The transmitter achieves 800 mV-ppd with 150 fs RJ while consuming 225 mW at 64 Gb/s.