Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation

As more sensitive data are shared, transmitted, and stored on electronic devices, data security has become an important concern. Encryption algorithms that are safe against software-based attacks still face security threats from side channel attacks. For example, an encryption device's power consumption or operational timing can be correlated to the data being processed by the device, which can give away the device's secret key. Dual-spacer Dual-rail Delay-insensitive Logic (D3L) is an IC design methodology that has been proved effective in mitigating power and timing attacks; however, large energy and area overheads of D3L circuits have hindered their applicability. In this paper an IC design methodology named Multi-Threshold D3L (MTD3L) is presented that achieves all D3L security advantages with considerably reduced overhead.