A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications

This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.