ESD failure mechanism and optimiztion for the LDMOS with low on-resistance and large geometric array used as output device

In this work, a novel ESD failure mechanism for the LDMOS with low on-resistance and large geometric array used as output device is presented. A novel structure based on the failure mechanism is also proposed to improve its ESD robustness. The secondary break current (It2) of the modified LDMOS is increased by almost 50% without changing other characteristics basically.