A built-in method for measuring the delay of TSVs in 3D ICs

This paper proposes a built-in delay measurement (BIDM) technique to measure the delay of through-silicon via (TSV) in the phase of post-bond test. The BIDM circuit can be shared by multiple TSVs such that the area overhead of the BIDM circuit is minimized. Furthermore, a measurement flow is proposed to eliminate the delay of interconnection between two TSVs such that the BIDM accuracy is not worsened with the increased number of measured TSVs. Experimental results show that the deviation of the result of BIDM and Hspice simulation is about 2.7%. Furthermore, a low-cost delay measurement element is proposed. In comparison with a typical Vernier delay line, the proposed delay measurement element can achieve 18% area reduction. In comparison with the ring-oscillator-based delay measurement method, the proposed BIDM has the features of low error and low cost, but needs long measurement time.