A novel vision chip architecture for image recognition based on convolutional neural network

This paper presents a novel vision chip architecture for high accuracy image recognition based on the state-of-the-art algorithm — convolutional neural network (CNN). The architecture consists three hierarchical parallel processors: a processing element (PE) array, a row processor (RP) array and a dual-core microprocessor (MPU). It is compatible with conventional algorithms and reconfigurable for computing convolutional neural networks effectively. The architecture was implemented on a FPGA platform with 50MHz system clock, it achieves high classification accuracy up to 96.3% and high frame rate more than 1600fps. Experiment results indicate that the vision system can achieve real-time performance for image recognition applications.