CMOS image sensor with programmable compressed sensing

The concept of compressed sensing CMOS image sensor is to compress data while sampling and prior to storage. This is our main idea to accomplish high speed imaging. In this paper, a CMOS image sensor with compressed sensing sampling mode is presented, which is composed of 256x256 pixel array. In order to reduce the complexity of the pseudo-random sequence generating circuits and reconstruction algorithm, the whole system is divided into 256 sub blocks. Each block consists of 16x16 pixel array with a single sigma-delta ADC, which is used to achieve the linear transformation. Similar to the conventional column ADC, the sigma-delta ADC is also used to quantize the transformed results. We have made a simulation for the proposed imaging architecture based on a 256x256 lena image. The simulation results show that the PSNR of the recovery image reaches 31.58 dB, 29.86 dB, and 29.52 dB, while the compressed ratio is 1/2, 1/4, and 1/6 respectively. Thus the corresponding frame rate can be increased by 2, 4, and 6 folds.