Comparative analysis of different lottery bus arbitration techniques for SoC communication

System on Chip (SoC) integrates heterogeneous elements like memory, DSPs, timing sources, ADCs, DACs etc. on a silicon chip. One of the challenges in SoC communication is the presence of multiple master which competes for the same shared resources like bus, memory etc. at the same time. Bus arbitration techniques resolve this issue by allowing only one master, among the contending master to have access to the bus for communication purpose. There are different techniques to select among the contending masters like round robin, TDMA etc. But these techniques causes starvation and wasting of bus cycles which results in latency. Lottery bus arbitration tends to solve this issue by randomly selecting any one lottery ticket that are allocated to the master statically or dynamically. Dynamic lottery bus arbitration improves the waiting time of the bus master but, they are more complex as compared to static one. Special logic is required to calculate lottery ticket of each bus master at run time that adds to the complexity. This paper presents HDL implementation of static and dynamic lottery bus arbitration techniques using different alternatives that can be used to improve the waiting time of bus master in dynamic and static Lottery bus architecture. Comparative analysis is performed using Xilinx Vivado Webpack 15.2 for obtaining simulation results, synthesis and power reports. The results indicates that dynamic lottery bus arbitration technique is much more efficient, as it doesn't keep the ticket values of the bus master fixed, but complex compared to static lottery bus arbitration. Also, rotating priority lottery bus arbitration keeps the waiting time, on an average, of bus master very low when compared to other design approaches.