An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation

This work presents a 1.9~5.6 GHz fractional-N DPLL with digi-phase spur canceller. It utilizes a ramp signal generated from the fractional-N accumulator to automatically calibrate the TDC linearity. The chip also includes an MMD that overcomes the division ration skipping problem associated with the prior art MMDs. The ADPLL achieves a worst fractional spur level of -55 dBc and an in-band phase noise of -109 dBc/Hz (0.63 ps integrated jitter) while consuming 9.9 mW.