FPGA implementation of conventional and vedic algorithm for energy efficient multiplier

Digital Signal Processor (DSP) as well as other microcontroller applications requires fast and low power consumption systems to compete with the advanced technology. The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system it is required to have high speed and low power consumption multiplier. In this paper we proposed the comparative study of two different algorithms, first one is the conventional method called as “Booth Multiplier” and other is the vedic method “Nikhilam Navatascaram Dasatah” using reversible logic gates. Both the multipliers are designed and implemented by using Xilinx 13.2 ISE simulator. Comparative results of both the multipliers are analyzed in terms of delay, area and power consumption.