New QVCO design using UTBB FDSOI technology

Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology. To overcome the problem induced by aggressive technological 28nm node and beyond, the solutions are undoped channel devices. Two silicon technologies have emerged: FinFET and FDSOI. We have introduced the UTBB FDSOI technology in our lectures and practical activities under Cadence Labs. In this paper, we present a new inverter topology decreasing the process variability influence on performances of a ring oscillator. Using FDSOI technology, we propose a new complementary structure based on a pair of Back-gate cross-coupled inverters offering a fully symmetrical operation of complementary signals. Finally, we have studied the jitter of such ring oscillator and proposed some explanations.