Navigating PCB stackup layer assignments for optimized si and pi performance in high speed, high power designs

Demanding signal- and power-integrity performance requirements in high-performance computing (HPC) systems require careful trade-space analysis when prioritizing layer allocations in printed circuit board (PCB) designs. Typically, the topmost layers in a stackup construction are the most desirable for enhancing both signal and power delivery capabilities. In this paper, we use analytical performance metrics to determine PCB layer utilization for optimized signal and power performance in sample designs targeting 56 Gbps non-return-to-zero (NRZ) differential signaling and a power delivery network (PDN) providing sub-1 mOhm impedance.