Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques

In this study, various fault tolerant techniques have been handled for pipelined MIPS-32 microprocessor in order for correct operation in the presence of faults and reliability analysis have been performed. For this purpose, register file is focussed on due to the fact that it is one of the most important unit of microprocessor. Register files designed with the fault tolerant methods have been synthesized with Cadence RTL Compiler, area and maximum frequency results have been obtained based on TSMC-90 nm technology. Mathematical models have been presented with the assumption that transient faults occur with a Poisson distribution and bit failures are statistically independent for reliability analysis. The results and graphics have been given by using Octave.