Logic characterization vehicle design for yield learning

A comprehensive investigation of new integrated circuit (IC) design and fabrication technologies is crucial for yielding reliable ICs. This work describes the state of a novel test chip design methodology that results in a test chip referred to as the Carnegie Mellon Logic Characterization Vehicle (CM-LCV). Experiments show that the CM-LCV is able to achieve single stuck line fault coverage of up to 99.4% using an optimal, minimal test set.