Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience

SRAM-based Field Programmable Gate Arrays (FP-GAs) have been used in the aerospace application for more than a decade. Unfortunately, a significant disadvantage of these devices is their sensitivity to radiation effects that can cause bit flips in memory elements and ionisation induced faults in semiconductors, commonly known as Single Event Upsets (SEUs). An early dependability analysis on SRAM FPGA-based safety-critical application will enable the designers to develop a more reliable and robust design complying with design requirements, such as the DO-254 standard. We propose a methodology based on probabilistic model checking, to analyze the dependability and performability properties of such designs to guide design decisions. Probabilistic model checking is a well known formal verification technique, and the main advantage is that the analysis is exhaustive, which results in numerically exact answers to the temporal logic queries that contrast with discrete-event simulations. In the proposed methodology, starting from the high-level description of a system, a Markov (reward) model is constructed from the extracted Control Data Flow Graph (CDFG). Various dependability and performability related properties are then verified automatically using the PRISM model checker tool.