Effective Drive Current for Pass-Gate Transistors

A two-point expression of effective drive current (I
_eff
_PG) for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of I
_eff
_PG estimates the PG latency with a reasonable accuracy (relative error <;15%) under different technology nodes from 90 to 20 nm and a wide range of biasing conditions including gate overdrive voltage up to 0.4 V and nonzero body bias between -0.3 and 0.3 V. The effective drive current expression is simple to use, independent of process technologies, and maintains accuracy when transistors are scaled down to deep submicron regime with severe nonidealities such as drain-induced barrier lowering. I
_eff
_PG provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current (I
_{eff_inv}
) is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of I
_eff
_PG is discussed, which illustrates the I
_eff
_PG does not improve from device scaling as much as CMOS saturation current (I
_dsat
) and effective drive current (I
_{eff_inv}
) do.