Photolithography study for advanced packaging technologies

In recent years, demand for high density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution processes over chip size has become a hot topic these days. Canon has identified key challenges that must be solved for success of high density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool which is now widely used at customer sites. In this paper, we will explain details of FPA-5510iV features that support high density integration, additional challenges that must be solved for successful implementation of high-density integration technologies in mass production and Canon's efforts to solve the remaining challenges.