Compact modeling and simulation of TSV with experimental verification

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σ
_θ
|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.