An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm

SIFT algorithm is the most popular and widely used computer vision method for image feature extraction, because of its excellent robustness for various transformations, while the computational burden and huge hardware requirements limit the applications of SIFT algorithm, especially for the real-time and energy-efficient embedded machine vision systems. In this paper, a hardware accelerator of analog circuit network for the Gaussian scale space establishment has been proposed, which is the most computationally expensive of SIFT algorithm. The accelerator adopts a current-mode circuit network operating in sub-threshold region, so that the power dissipation can be very low. Moreover, extensive repetitive multiplication and addition operations are completed in analog domain directly, before the original data is transformed to digital domain by ADC. Thus, the calculation time is approximately equal to the settling time of circuit network, which is usually down to several nano-seconds. Simulations with standard CMOS process have demonstrated that the processing speed is about 400 ps/pixel, while the power consumption is only 1.8 mW. The overall processing speed for VGA-format (640*480) image is up to 600 fps, which is at least 27X faster than the state-of-art digital counterparts systems.