Device/system performance modeling of stacked lateral NWFET logic

New device structures using two layers of lateral nanowire transistors (LFET) stacked on top of each other are proposed for an inverter and 2-input NAND (NAND2) gate. By stacking PFETs on top of NFETs, the effective cell footprint areas of an inverter and a NAND2 are reduced by 50% and 33%, respectively. In this paper, parasitic modeling and system-level simulations are performed for the proposed structures. Based on the capacitance simulations, the stacked structure provides a 13% reduction in input gate capacitance for a minimum sized inverter thanks to a shorter vertical NFET cell. The system-level simulation results show up to 12.9% of the power saving at the supply voltage of 0.6V.