Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis

Whereas contemporary Last Level Cache (LLC) designs occupy a significant fraction of total die area in chip-multiprocessors (CMPs), approaches to deal with the vulnerability increase of LLC against Single Event Upset (SEU) and Multi-Bit Upsets (MBUs) are sought. In this paper, we focus on reliability assessment of eDRAM LLC to propose a more accurate and application-relevant vulnerability estimation approach compared to conventional LLC SEU analysis methods. In particular, the eDRAM Bit Upset Vulnerability Factor (BUVF) is proposed and an algorithm is developed to assess its behavior for soft errors using experimental benchmark suites. BUVF explicitly targets the vulnerable portion of the eDRAM refresh cycle where the critical charge varies depending on write voltage, storage and bit-line capacitance. Results for the PARSEC benchmark suite indicated that vulnerable sequences account for about 27.2% of data array lifetime in the cache, among which the Read-Read (RR) access sequence contributes about 23.4%. Furthermore, regardless of the size of the vulnerable data set located in an RR sequence over a short interval, the corresponding region of cache is seen to contribute negligible vulnerability to BUVF, which results from spending a small fraction of program execution time undergoing RR sequences. We recast the problem of reliable eDRAM LLC design as a straightforward search for reduced BUVF.